There are many types of busses used in computing systems. For example: a system bus between several processors and a memory controller; a system cluster bus among several link chips of various systems; a memory bus between several dynamic random access memory (DRAM) reporting chips and a memory controller; a DRAM bus linking several dual-inline memory modules (DIMMs) to its reporting chip; a common program peripheral component interface (PCI) bus linking PCI bridge chips, PCI bus slave and PCI master together.
These buses generally use two major signal routing schemes: (1) OTA—one agent to all other agents; or (2) OTO—one agent to only one agent on the bus. For the routing schemes, there is a requirement that there be one signal per signal I/O pin.
A figure of merit for signal routing schemes is I/O pin data efficiency. A high I/O pin data efficiency means more data transfer per I/O pin. I/O pin data efficiency is a product of signal I/O pin efficiency and data frequency efficiency.
A common use of these signal routing schemes for busses described above is a distributed network or distributed net. FIG. 1 is a block schematic diagram of a prior art distributed net 100. Net 100 includes a main signal line 105, a signal I/O pin 105A and a plurality of stubs 110. All agents 115 are attached to main signal line 105 by a stub 110 with one signal I/O pin 115A. Net 100 thus includes one I/O pin 1115A per distributed net. Any single agent 115 sends data and commands to any other agent over signal line 105 thru I/O pin 115A. There are several different configurations for net 100 that have been used: a double end termination distributed net 100 (used as a system bus); a serial termination (SSTL) distributed net 100 (used as a DDR memory bus); and an open end distributed net 100 (used for PCI bus) are examples of the versatility of the prior art system. However, in terms of operation frequency, distributed net 100 is far from ideal. The characteristics of net 100 that limit the frequency that the signals may be carried over net 100 include the plurality of positive and negative reflection points along the signal paths and the phase shifts that are introduced by the stub lines. Each middle agent has an open end that is a positive reflection point and each stub-to-main-line intersection is a negative reflection point. The length of each stub line introduces a phase shift for signals propagating down main line 105, with longer stub lines 110 causing a larger phase shift. The result is that signals of distributed net 100 usually exhibits significant undershoot/overshoot, rise time degradation ad irregular phase shift. These effects effectively limit the operational frequency of distributed net 100, which degrades the IO data efficiency of distributed net 100.
Accordingly, what is needed is a system and method for improved IO data efficiency as compared to the distributed network scheme of the prior art. The present invention addresses such a need thru maintaining I/O pin efficiency but increasing the data frequency efficiency.